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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2005-2007, zarlink semiconductor inc. all rights reserved. features ? full duplex transcoder with four encode channels and four decode channels ? 32 kbps, 24 kbps and 16 kbps adpcm coding complying with itu-t (previously ccitt) g.726 (without 40 kbps), and ansi t1.303-1989 ? low power operation, 6.5 mw typical ? asynchronous 4.096 mhz master clock operation ? ssi and st-bus interface options ? transparent pcm bypass ? transparent adpcm bypass ? linear pcm code ? no microprocessor control required ? simple interface to codec devices ? pin selectable ? law or a-law operation ? pin selectable itu-t or signed magnitude pcm coding ? single 3.3 volts power supply applications ? pair gain ? voice mail systems ? wireless telephony systems description the quad adpcm transcoder is a low power, cmos device capable of four encode and four decode functions per frame. four 64 kbps pcm octets are compressed into four 32, 24 or 16 kbps adpcm words, and four 32, 24 or 16 kbps adpcm words are expanded into four 64 kbps pcm octets. the 32, 24 and 16 kbps adpcm transcoding algorithms utilized conform to itu-t recommendation g.726 (excluding 40 kbps), and ansi t1.303 - 1989. january 2007 ordering information zl38010dce 28 pin soic tubes ZL38010DCF 28 pin soic tape & reel zl38010dce1 28 pin soic** tubes ZL38010DCF1 28 pin soic** tape & reel **pb free matte tin -40 c to +85 c zl38010 low power quad adpcm transcoder data sheet figure 1 - functional block diagram adpcm i/o pcm i/o control decode vdd vss pwrdn ic ms1 ms2 a/ format ms5 ms4 ms3 ms6 linear sel timing adpcmi adpcmo enb1 enb2/f0od bclk f0i mclk c2o en1 en2 pcmo1 pcmi1 pcmo2 pcmi2 full duplex quad transcoder
zl38010 data sheet 2 zarlink semiconductor inc. switching, on-the-fly, between 32 kbps and 24 kbps adpcm, is possible by controlling the appropriate mode select (ms1 - ms6) control pins. all optional functions of the device are pin sele ctable allowing a simple interface to industry standard codecs, digital phone devices and layer 1 transceivers. linear coded pcm is provided to facilitate external dsp functions. change summary changes from october 2005 issue to january 2007 issue. figure 2 - pin connections pin description page item change 1 ordering information box added pb free part numbers. pin # name description 1en1 enable strobe 1 (output). this 8 bit wide, active high strobe is active during the b1 pcm channel in st-bus mode. becomes a si ngle bit, high true pulse when linear=1. in ssi mode this output is high impedance. 2mclk master clock (input). this is a 4.096 mhz (minimum ) input clock utilized by the transcoder function; it must be supplied in both st-bus and ssi modes of operation. in st-bus mode the c4 st-bus clock is applied to this pin. this synchronous clock is also used to control the data i/o flow on the pcm and adpcm input/output pins according to st-bus requirements. in ssi mode this master cloc k input is derived from an external source and may be asynchronous with respect to the 8 khz fr ame. mclk rates greater than 4.096 mhz are acceptable in this mode since the data i/o rate is governed by bclk. 3f0i frame pulse (input). frame synchronization pulse in put for st-bus operation. ssi operation is enabled by c onnecting this pin to v ss . 4c2o 2.048 mhz clock (output). this st-bus mode bit clock output is the mclk (c4 ) input divided by two, inverted, and synchronized to f0i . this output is high-impedance during ssi operation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 ms1 vdd ms3 ic ms4 format ms2 pwrdn adpcmi adpcmo ms5 ms6 en2 pcmo1 bclk pcmi1 linear enb2/f0od vss c2o mclk f0i pcmi2 enb1 pcmo2 en1 sel a/
zl38010 data sheet 3 zarlink semiconductor inc. 5bclk bit clock (input). 128 khz to 4096 khz bit clock input for both pcm and adpcm ports; used in ssi mode only . the falling edge of this clock latches data into adpcmi, pcmi1 and pcmi2. the rising edge clocks data out on adpcmo, pcmo1 and pcmo2. this input must be tied to v ss for st-bus operation. 6pcmo1 serial pcm stream 1 (output). 128 kbps to 4096 kbps serial companded/linear pcm out- put stream. data are clocked out by rising edge of bclk in ssi mode. clocked out by mclk divided by two in st-bus mode. see figure 14. 7pcmi1 serial pcm stream 1 (input). 128 kbps to 4096 kbps serial companded/linear pcm input stream. data are clocked in on falling edge of bclk in ssi mode. clocked in at the 3/4 bit position of mclk in st-bus mode. see figure 14. 8v ss digital ground. nominally 0 volts 9 linear linear pcm select (input) . when tied to v dd the pcm i/o ports (pcm1,pcm2) are 16- bit linear pcm. linear pcm operates only at a bit rate of 2048 kbps. companded pcm is selected when this pin is tied to v ss . see figure 5 & figure 8. 10 enb2/f0od pcm b-channel enable strobe 2 (inpu t) / delayed frame pulse (output). ssi operation: enb2 (input). an 8-bit wide enable strobe input defining b2 channel (ad)pcm data. a valid 8-bit strobe must be pr esent at this input fo r ssi operation. see figure 4 & figure 6. st-bus operation: f0od (output). this pin is a delayed frame strobe output. when lin- ear=0, this becomes a delayed frame pulse output occurring 64 c4 clock cycles after f0i and when linear = 1 at 128 c4 clock cycles after f0i . see figures 7, 8, 9 & 14. 11 enb1 pcm b-channel enable strobe 1 (input). ssi operation: an 8-bit wide enable strobe input defining b1 chan nel (ad)pcm data. a valid 8-bit strobe must be present at this input for ssi operation. st-bus operation: when tied to v ss transparent bypass of the st-bus d- and c- chan- nels is enabled. when tied to v dd the st-bus d-channel and c-channel output timeslots are forced to a high-impedance state. 12 pcmo2 serial pcm stream 2 (output). 128 kbps to 4096 kbps serial companded/linear pcm out- put stream. clocked out by rising edge of bclk in ssi mode. clocked out by mclk divid- ed by two in st-bus mode. see figure 14. 13 pcmi2 serial pcm stream 2 (input). 128 kbps to 4096 kbps serial companded/linear pcm input stream. data bits are clocked in on falling ed ge of bclk in ssi mode. clocked in at the 3/4 bit position of mclk in st-bus mode. see figure 14. 14 sel select (input). pcm bypass mode: when sel=0 the pcm1 port is selected for pcm bypass operation and when sel=1 the pcm2 port is selected for pcm bypass operation. see figure 6 & figure 9. 16 kbps transcoding mode: ssi operation - in 16 kbps transcoding mode, the adpcm words are assigned to the i/o timeslot defined by enb2 when sel=1 and by enb1 when sel=0. see figure 4. st-bus operation- in 16 kbps transcoding mode, the adpcm words are assigned to the b2 timeslot when sel=1 and to the b1 timeslot when sel=0. see figure 9. pin # name description
zl38010 data sheet 4 zarlink semiconductor inc. note: all unused inputs should be connected to logic low or high unles s otherwise stated. all outputs should be left open circuit whe n not used. all inputs have ttl compatib le logic levels except for mclk which ha s cmos compatible logic levels and pwrdn which has schmitt trigger compatible logic levels. all outputs are cmos with cmos logic leve ls (see dc electrical characteristics). 15 a/ a-law/ ? law select (input). this input pin selects ? law companding when set to logic 0, and a-law companding when set to logic 1. this control is for all channels.this input is ignored in linear mode dur ing which it may be tied to v ss or v dd . 16 format format select (input). selects itu-t pcm coding when high and sign-magnitude pcm coding when low. this control is for all channels.this input is ignored in linear mode during which it may be tied to v ss or v dd . 17 pwrdn power-down (input). an active low reset forcing the device into a low power mode where all outputs are high-impedance and device operation is halted. 18 ic internal connection (input). tie to v ss for normal operation. 19 20 21 ms1 ms2 ms3 mode selects 1, 2 and 3 (inputs). mode selects for all four encoders. ms3 ms2 ms1 mode 0 0 0 32 kbps adpcm 0 0 1 24 kbps adpcm 0 1 0 16 kbps adpcm in en1/enb1 when sel=0 in en2/enb2 when sel=1 0 1 1 adpcm bypass for 32 kbps and 24 kbps 1 0 0 adpcm bypass for 16 kbps 1 0 1 pcm bypass (64 kbps) to pc m1 if sel=0, pcm2 if sel=1 1 1 0 algorithm reset (itu-t optional reset) 1 1 1 adpcmo disable 22 v dd positive power supply. nominally 3.3 volts +/-10% 23 adpcmi serial adpcm stream (input). 128 kbps to 4096 kbps serial adpcm word input stream. data bits are clocked in on falling edge of bclk in ssi mode and clocked in on the 3/4 bit edge of mclk in st-bus mode. 24 adpcmo serial adpcm stream (output). 128 kbps to 4096 kbps serial adpcm word output stream. data bits are clocked out by rising edge of bclk in ssi mode and clocked out by mclk divided by two in st-bus mode. 25 26 27 ms4 ms5 ms6 mode selects 4, 5 and 6 (inputs). mode selects for all four decoders. ms6 ms5 ms4 mode 0 0 0 32 kbps adpcm 0 0 1 24 kbps adpcm 0 1 0 16 kbps adpcm in en1/enb1 when sel=0 in en2/enb2 when sel=1 0 1 1 adpcm bypass for 32 kbps and 24 kbps 1 0 0 adpcm bypass for 16 kbps 1 0 1 pcm bypass (64 kbps) to pc m1 if sel=0, pcm2 if sel=1 1 1 0 algorithm reset (itu-t optional reset) 1 1 1 pcmo1/2 disable 28 en2 enable strobe 2 (output). this 8 bit wide, active high strobe is active during the b2 pcm channel in st-bus mode. forced to high impedance when linear=1. pin # name description
zl38010 data sheet 5 zarlink semiconductor inc. functional description the quad-channel adpcm transcoder is a low power, c mos device capable of four encode and four decode operations per frame. four 64 kbps channels (pcm octets) are compressed into four 32, 24 or 16 kbps adpcm channels (adpcm words), and four 32, 24 or 16 kbps adpcm channels (adpcm words) are expanded into four 64 kbps pcm channels (pcm octets). the adpcm tr anscoding algorithm utiliz ed conforms to itu-t recommendation g.726 (excluding 40 kbps), and ansi t1 .303 - 1989. switching on-the-fly between 32 and 24 kbps transcoding is possible by toggli ng the appropriate mode select pins (supports t1 robbed- bit signalling). all functions supported by the device are pin selectable . the four encode functions comprise a common group controlled via mode select pins ms1, ms2 and ms3. simila rly, the four decode functions form a second group commonly controlled via mode select pins ms4, ms5 and ms 6. all other pin controls are common to the entire transcoder. the device requires 6.5 mwatts (mclk= 4.096 mhz) typica lly for four channel tran scode operation. a minimum master clock frequency of 4.096 mhz is required for the circuit to complete four encode channels and four decode channels per frame. for ssi operati on a master clock frequency greater than 4.096 mhz and asynchronous, relative to the 8 khz frame, is allowed. the pcm and adpcm serial busses support both st-bus and synchronous serial interface (ssi) operation. this allows serial data clock rates from 128 khz to 4096 khz, as well as compatibility with zarlink?s standard serial telecom bus (st-bus). for st-bus operation, on chip channel counters provide c hannel enable outputs as well as a 2048 khz bit clock output whic h may be used by down -stream devices utilizing the ssi bus interface. linear coded pcm is also supported. in this mode the encoders compress, four 14-bit, two?s complement (s,s,s,12,...,1,0), uniform pcm channels into four 4, 3 or 2 bit adpcm channels. similarly, the decoder expands four 4, 3 or 2 bit adpcm channels into four 16-bit, tw o?s complement (s,14,...,1,0), uniform pcm channels. the data rate for both st-bus and ssi operation in this mode is 2048 kbps.
zl38010 data sheet 6 zarlink semiconductor inc. serial (ad)pcm data i/o serial data transfer to/from the quad adpcm transcode r is provided through one adpcm and two pcm ports (adpcmi, adpcmo, pcmi1, pcmo1, pcmi2, pcmo2). data is transferred through these ports according to either st-bus or ssi requirements. the device determines the mode of operation by monitoring the signal applied to the f0i pin. when a valid st-bus frame pulse (24 4nsec low going pulse) is applied to the f0i pin the transcoder will assume st-bus operation. if f0i is tied continuously to v ss the transcoder will assu me ssi operation. pin functionality in each of these modes is described in the following sub-sections. st-bus mode during st-bus operation the c2o, en1, en2 and f0od outputs become active and all se rial timing is derived from the mclk (c4 ) and f0i inputs while the bclk input is tied to v ss . (see figures 7, 8 & 9.) basic rate ?d? and ?c? channels in st-bus mode, when enb1 is brought low, transparent transport of the st-bus "basic rate d- and c-channels" is supported through the pcmi1 and pcmo1 pins. this allows a microprocessor controlled device, connected to the pcmi/o1 pins, to access the "d" and "c" channels of a transmission device connected to the adpcmi/o pins. when enb1 is brought high, the ?d? and ?c? channel outputs are tristated. basic rate ?d? and ?c? channels are not supported in linear mode.(see figure 7.) ssi mode during ssi operation the bclk, enb1 and enb2/f0od inputs become active. the c2o, en1, and en2 outputs are forced to a high-impedance state except during linear operation during which the en1 output remains active. (see figures 4, 5 & 6.) the ssi port is a serial data interface, including data input and data output pi ns, a variable rate bit clock input and two input strobes providing enables fo r data transfers. there are three ssi i/o ports on the quad adpcm; the pcmi/o1 pcm port, the pcmi/o2 pcm port, and the adpc mi/o port. the two pcm ports may transport 8-bit companded pcm or 16-bit linear pcm. the alignment of the channels is determi ned by the two input strobe signals enb1 and enb2/f0od . the bit clock (bclk) and input strobes (enb1 and enb2/f0od ) are common for all three of the serial i/o ports. bclk can be any frequency betwe en 128 khz and 4096 khz synchronized to the input strobes. bclk may be discontinuous outside of the strobe bo undaries except when linear=1. in linear mode, bclk must be 2048 khz and continuous for 64 cycles after the enb1 rising edge and for the duration of enb2/f0od . mode select operation (ms1, ms2, ms3, ms4, ms5, ms6) mode select pins ms1, ms2 and ms3 program different bit rate adpcm c oding, bypass, algorithmic reset and disable modes for all four encoder functions simultaneously. when 24 kbps adpcm mode is selected bit 4 is unused while in 16 kbps adpcm mode all adpcm channel s are packed contiguously into one 8-bit octet. mode select pins ms4, ms5 and ms6 operate in the same manner for the four decode functions. the mode selects must be set up according to the timing constraints illustrated in figures 16 and 17. 32 kbps adpcm mode in 32 kbps adpcm mode, the 8-bit pcm octets of the b1, b2, b3 and b4 channels (pcmi1 and pcmi2) are compressed into four 4-bit adpcm words on adpcmo. conversely, the 4-bit adpcm words of the b1, b2, b3 and b4 channels from adpcmi are expanded into four 8-bit pcm octets on pcmo1 and pcmo2. the 8-bit pcm octets (a-law or -law) are transferred most significa nt bit first starting with b7 and ending with b0. adpcm words are transferred most significant bi t first starting with i1 and ending with i4 (see figures 4 & 7). reference itu-t g.726 for i-bit definitions.
zl38010 data sheet 7 zarlink semiconductor inc. 24 kbps adpcm mode in 24 kbps mode pcm octets are transcoded into 3-bit words rather than the 4-bit words utilized in 32 kbps adpcm. this is useful in situations where lower bandw idth transmission is requir ed. dynamic operation of the mode select control pins will allow switching from 32 kbps mode to 24 kbps mode on a frame by frame basis. the 8 bit pcm octets (a-law or -law) are transferred most significant bit first starting with b7 and ending with b0. adpcm words are transferred most significant bit first star ting with i1 and ending with i3 (i4 becomes don?t care). (see figures 4 & 7.) 16 kbps adpcm mode when sel is set to 0, the 8-bit pcm octets of the b1, b2, b3 and b4 channels (pcmi1 and pcmi2) are compressed into four 2-bit adpcm words on adpcmo during the enb1 timeslot in ssi mode and during the b1 timeslot in st- bus mode. similarly, the four 2-bit adpcm words on adpc mi are expanded into four 8-bit pcm octets (on pcmo1 and pcmo2) during the enb1/b1 timeslot. (see figures 4 & 7.) when sel is set to 1, the same conversion takes place as described when sel = 0 except that the enb2/b2 timeslots are utilized. a-law or -law 8-bit pcm are received and transmitted most si gnificant bit first starti ng with b7 and ending with b0. adpcm data are most significant bit firs t starting with i1 and ending with i2. adpcm bypass (32 and 24 kbps) in adpcm bypass mode the b1 and b2 channel adpcm words are bypassed (with a two-frame delay) to/from the adpcm port and placed into the most signi ficant nibbles of the pcm1/2 port oc tets. note that the sel pin performs no function for these two modes (see figures 6 & 9). linear, format and a/ pins are ignored in bypass mode. in 32 kbps adpcm bypass mode, bits 1 to 4 of the b1, b2, b3 and b4 channels from pcmi1 and pcmi2 are transparently passed, with a two frame delay, to the same channels on adpcmo. in the same manner, the b1, b2, b3 and b4 channels from adpcmi are transparently pa ssed, with a two frame delay, to the same channels on pcmo1 and pcmo2 pins. bits 5 to 8 are don?t care. this feature allows two voice terminals, which utilize adpcm transcoding, to communicate through a system without incurring unnecessary transcode conversions. this arrangement allows byte-wide or nibble-wi de transport through a switching matrix. 24 kbps adpcm bypass mode is the same as 32 kbps mode bypass excepting that only bits 1 to 3 are bypassed and bits 4 to 8 are don?t care. adpcm bypass (16 kbps) when sel is set to 0, only bits 1 and 2 of the b1, b2, b3 and b4 pcm octets (on pcmi1 and pcmi2) are bypassed, with a two frame delay, to the same channels on adpcmo during the enb1 timeslot in ssi mode and during the b1 timeslot in st-bus mode. similarly, the four 2-bit ad pcm words on adpcmi are transparently bypassed, with a two frame delay, to pcmo1 and pcmo2 during the enb1 or b1 timeslot. bits 3-8 are do n?t care. (see figures 6 & 9.) when sel is set to 1, the same bypass occurs as desc ribed when sel = 0 except that the enb2 or b2 timeslots are utilized. linear, format and a/ pins are ignored in bypass mode.
zl38010 data sheet 8 zarlink semiconductor inc. pcm bypass when sel is set to 0, the b1 and b2 pcm channels on pcmi1 are transparently passed, with a two-frame delay, to the same channels on the adpcmo. summarily, the two 8-bit words which are on adpcmi are transparently passed, with a two-frame delay, to channels b1 and b2 of pcmo1 while pcmo2 is set to a high-impedance state.(see figures 6 & 9.) when sel is set to 1, the b3 and b4 channels on pcmi2 are transparently passed, with a two frame delay, to the same channels on adpcmo. similarly, the two 8-bit words which are on adpcmi are transparently passed, with a two-frame delay, to channels b3 and b4 of pcmo2. in th is case pcmo1 is always high-impedance if enb1 = 0. if enb1 = 1 during st-bus operation then the d and c channels are active on pcmo1. linear, format and a/ pins are ignored in bypass mode. algorithm reset mode while an algorithmic reset is asserted the device will increm entally converge its internal variables to the 'optional reset values' stated in g.726. algorithmic reset requires that the master clock (mclk) and frame pulse (enb1/2 or f0i ) remain active and that the reset condition be valid for at least four frames. note that this is not a power down mode; see pwrdn for this function. adpcmo & pcmo1/2 disable when the encoders are programmed for adpcmo disable (ms1 to ms3 set to 1) the adpcmo output is set to a high impedance state and the internal encode function re mains active. therefore convergence is maintained. the decode processing function and data i/o remain active. when the decoders are programmed for pcmo1/2 disable (ms4 to ms6 set to 1) the pcmo1/2 outputs are high impedance during the b channel timeslots and also, during st-bus operation, the d and c channel timeslots according to the state of enb1. therefore convergence is maintained. the encode processing function and data i/o remain active. whenever any combination of the encoders or decoders are set to the disable mode the following outputs remain active. a) st-bus mode: enb2/f0od , en1, en2 and c2o. also the ?d? and ?c? channels from pcmo1 and adpcmo remain active if enb1 is set to 0. if enb1 is brought high then pcmo1 and adpcmo are fully tri-stated. b) ssi mode: when used in the 16-bit linear mode, only the en1 output remains active. for complete chip power down see pwrdn .
zl38010 data sheet 9 zarlink semiconductor inc. other pin controls 16 bit linear pcm setting the linear pin to logic one causes the device to change to 16-bit linear (uniform) pcm transmission on the pcmi/o1 and pcmi/o2 ports. the data rate for both st-b us and ssi operation in this mode is 2048 kbps and all decode and encode functions are affected by this pin. in ssi mode, the input channel strobes enb1 and enb2/f0od remain active for 8 cycles of bclk for an adpcm transfer. the en1 output is high for one bclk period at the end of the frame (i.e., during the 256 th bclk period). in st-bus mode, the output strobes en1 and enb2/f0od are adjusted to accommodate the required pcm i/ o streams. the en1 output becomes a single bit high true pulse during the last clo ck period of the frame (i.e., the 256 th bit period) while enb2/f0od becomes a delayed, low true frame-pulse (f0od ) output occurring during the 64 th bit period after the en1 rising edge. linear pcm on pcmi1 and pcmi2, are rece ived as 14-bit, two?s complement dat a with three bits of sign extension in the most significant positions (i.e ., s,s,s,12,...1,0) for a total of 16 bits. the linear pcm data transmitted from pcmo1 and pcmo2 are 16-bit, two?s complement data with one sign bit in the most si gnificant position (i.e., s,14,13,...1,0) 32 and 24 kbps adpcm mode in 32 kbps and 24 kbps linear mode, th e 16-bit uniform pcm dual-octets of th e b1, b2, b3 and b4 channels (from pcmi1 and pcmi2) are compressed into four 4-bit words on adpcmo. the four 4-bit adpcm words of the b1, b2, b3 and b4 channels from adpcmi are expanded into four 16-bit uniform pcm dual-octets on pcmo1 and pcmo2. 16-bit uniform pcm are received and transmitted most signi ficant bit first starting with b15 and ending with b0. adpcm data are transferred most significant bit first star ting with i1 and ending with i4 for 32 kbps and ending with i3 for 24 kbps operation (i.e., i4 is don?t care).(see figures 5 & 8.) 16 kbps adpcm mode when sel is set to 0, the four, 2-bit adpcm words ar e transmitted/received on adpc mo/i during the enb1 time- slot in ssi mode and during the b1 timeslot in st-bus mode. when sel is set to 1, the four, 2-bit adpcm words are transmitted/received on adpcmo/i dur ing the enb2 timeslot in ssi mode and during the b2 timeslot in st-bus mode. (see figures 5 & 8.) pcm law control (a/ , format) the pcm companding/coding law invoked by the transcoder is controlled via the a/ and format pins. itu-t g.711 companding curves, -law and a-law, are selected by the a/ pin (0= -law; 1=a-law). per sample, digital code assignment can conform to itu-t g.711 (when format=1) or to sign-magnitude coding (when format=0). table 1 illustrates these choices.
zl38010 data sheet 10 zarlink semiconductor inc. table 1 - companded pcm power down setting the pwrdn pin low will asynchronously cause all internal operation to halt and the device to go to a power down condition where no internal cl ocks are running. output pins c2o, en1, en2, pcmo1, pcmo2 and adpcmo and i/o pin f0od /enb2 are forced to a high-impedance state. following the reset (i.e., pwrdn pin brought high) and assuming that clocks are applied to the mclk and bclk pins, t he internal clocks will still not begin to operate until the first frame alignment is detected on the enb1 pin for ssi mode or on the f0i pin for st-bus mode. the c2o clock and en1, en2 pins will not start operation until a valid fr ame pulse is applied to the f0i pin. if the f0i pin remains low for longer than 2 cycles of mclk then the c2o pin will top toggling and will stay low. if the f0i pin is held high then the c2o pin will continue to operate. in st-bus mode the en 1 and en2 pins will stop toggling if the frame pulse (f0i ) is not applied every frame. master clock (mclk) a minimum 4096 khz master clock is required for executio n of the transcoding algorit hm. the algorithm requires 512 cycles of mclk during one frame fo r proper operation. for ssi operation th is input, at the mclk pin, may be asynchronous with the 8 khz frame prov ided that the lowest frequency and devia tion due to clock jitter still meets the strobe period requirem ent of a minimum of 512 t c4p - 25%t c4p (see figure 3). for example, a system producing large jitter values can be accommodated by running an over-speed mclk that will ensure a minimum 512 mclk cycles per frame is obtained. the mi nimum mclk period is 61 nsec, which translates to a maximum frequency of 16.384 mhz. extra mclk cycles (>512/frame) are acceptab le since the transcoder is aligned by the appropriate strobe signals each frame. figure 3 - mclk minimum requirement format 01 pcm code sign- magnitude a/ = 0 or 1 itu-t (g.711) (a/ = 0) (a/ = 1) + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 - zero 0000 0000 0111 1111 0101 0101 - full scale 0111 1111 0000 0000 0010 1010 enb1 mclk 512 t c4p - 25%t c4p minimum
zl38010 data sheet 11 zarlink semiconductor inc. bit clock (bclk) for ssi operation the bit rate, for both adpcm and pcm ports, is determined by the clock input at bclk. bclk must be eight periods in duration and synchronous with the 8 khz frame inputs at enb1 and enb2. data is sampled at pcmi1/2 and at adpcmi conc urrent with the falling edge of bclk. data is available at pcmo1/2 and adpcmo concurrent with the rising edge of bclk. bclk may be any rate between 128 khz and 4096 khz. for st- bus operation bclk is ignored (tie to v ss ) and the bit rate is internally set to 2048 kbps. figure 4 - ssi 8-bit companded pcm relative timing adpcm i/o bclk enb1 enb2/f0od pcmi/o1 adpcm i/o sel = 0 sel = 1 32 kbps 24 kbps 16 kbps sel for 16 kbps only b1 b2 pcmi/o2 1234 b1 b2 123x b1 b2 12 b3 b4 12 12 12121212 12 765 3 4210 b3 b4 1234 123x 1234 b3 b4 123x 1234 123x b1 b2 b3 b4 765 3 4210 765 3 4 210765 3 4210 x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel strobe boundaries
zl38010 data sheet 12 zarlink semiconductor inc. figure 5 - ssi 16-bit linear pcm relative timing enb1 enb2/f0od en1 adpcm i/o adpcmi/o b 1 1234 1234 1234 1234 123x 123x 123x 123x 12 sel = 1 sel = 1 sel = 0 bclk ... sel for 16 kbps only (2.048 mhz only) pcmi/o1 pcmi/o2 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 b1 b2 s = 3 bits sign extension ? law is 13 bit 2?s complement data (bits 0 -12) a-law is 12 bit 2?s complement data (shifted left once and utilizing bits 1 - 12, bit 0 not defined) 32 kbps 24 kbps 16 kbps b3 b4 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 notes: b 2 b 3 b 4 12 12 12 b 1 12 b 2 b 3 b 4 12 12 12 b1 b2 b3 b4 1234 1234 123x 123x b3 b4 b 1 12 b 2 b 3 b 4 12 12 12 x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel strobe boundaries
zl38010 data sheet 13 zarlink semiconductor inc. figure 6 - ssi pcm and adpcm bypass relative timing adpcmo/i bclk enb1 enb2/f0od pcmi/o1 765 3 4210 b1 b2 765 3 4 210 pcmi/o2 765 3 4210 b3 b4 765 3 4 210 765 3 4210 765 3 4 210 sel = 0 adpcmo/i pcmi/o1 123 x 4xxx sel = 1 b1 b2 pcmi/o2 b3 b4 sel = 0 123 x 4xxx 123 x 4xxx 12341234 1234 1234 adpcm o/i pcmi/o1 pcmi/o2 12x x xxxx b1 b2 b3 b4 12x x xxxx 12x x xxxx12xx xxxx 12121212 1212 1212 b1 b2 b3 b4 b1 b2 b3 b4 32 kbps using bits 1 2 3 4 24 kbps where bit 4 = x 16 kbps ssi pcm bypass ssi adpcm bypass sel = 1 123 x 4xxx x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel strobe boundaries
zl38010 data sheet 14 zarlink semiconductor inc. figure 7 - st-bus 8-bit companded pcm relative timing mclk (c4 ) f0i adpcmi adpcmo c2o (output) b1 b2 b3 b4 en1 (output) en2 (output) pcmi2 pcmo2 b3 b4 pcmi1 pcmo1 b1 b2 dc d c b1 sel=0 sel=1 b2 b4 b3 b1 b2 b4 b3 b1 b2 b4 b3 b1 b2 b4 b3 32 kbps is shown in 24 kbps, bit 4 becomes ?x? 16 kbps sel operates for enb2/f0od 76 54 76 543 210 321 0 76 54 76 543 210 321 0 7654 7654 321 0 321 0 01 76 543 210 121 21 21 2 121 21 21 2 121 21 212 121 21 212 123 4 123 4 123 4 123 4 76 54 76 543 210 321 0 01 7654 321 0 transparent relay of d- and c- channels when enb1=0 01 76543 210 123 4 123 41 23 4 1 234 01 76 543 210 outputs = high impedance inputs = don?t care x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel boundaries 16 kbps only
zl38010 data sheet 15 zarlink semiconductor inc. figure 8 - st-bus 16-bit linear pcm relative timing mclk (c4i ) f0i c2o adpcmi/o note: d &c channels not supported in this mode. sel operated for pcmi/o1 pcmi/o2 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 sss 12 11 10 9 8 7 6 5 4 3 2 1 0 b1 b2 b3 b4 adpcmi/o (32/24 kbps) (16 kbps) f0od /enb2 en1 (output) bit 4 = x at 24 kbps b 1 12 sel = 1 sel = 0 b 2 b 3 b 4 12 12 12 b 1 12 b 2 b 3 b 4 12 12 12 1234 1234 1234 1234 b1 b2 b3 b4 16 kbps only outputs = high impedance inputs = don?t care x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel boundaries
zl38010 data sheet 16 zarlink semiconductor inc. figure 9 - st-bus pcm and adpcm bypass relative timing en1 (output) en2 (output) mclk f0i c2o adpcmi adpcmo sel=0 sel=1 pcmi1 pcmo1 b1 b2 dc pcmi2 pcmo2 b3 b4 b1/b3 b2/b4 dc adpcmi/o adpcmi/o b3 b4 pcmi/o1 pcmi/o2 d c b1 b2 dc b3 b4 b1 b2 32 kbps 24 kbps bit 4 = x (16 kbps) pcmi/o1 pcmi/o2 d c b1 sel=0 sel=1 b2 b4 b3 b3 b4 c d xxx x b2 b1 01 01 01 p c m b y p a s a d p c m b y p a s xxxx 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 x x x x x x b1 b2 b4 b3 1 2 x x x x x x 1 2 x x x x x x 1 2 x x x x x x 1 2 3 4 xxxx 1 2 3 4 xxxx 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 enb2/f0od outputs = high impedance inputs = don?t care x = undetermined logic level output; don?t care input two frame delay from data input to data output outputs high impedance outside of channel boundaries
zl38010 data sheet 17 zarlink semiconductor inc. processing delay through the device in order to accommodate variable rate pcm and adpcm inte rfaces, the serial input an d output streams require a complete frame to load internal shift registers. intern al frame alignment of the en coding/decoding functions are taken from either of the f0i or enb1 & enb2 input strobes depending upon the device operating mode (i.e., st- bus or ssi). the encoding/decoding of all channels then takes one frame to co mplete before the output buffers are loaded. this results in a two frame transcoding delay. th e two frame delay also applies to the d and c channels and to the pcm and adpcm bypass functions.(see figure 10.) note: when changing the relative positions of the enb1 and enb2 strobes, precaution must be taken to ensure that two conditions are met. they are: 1. there must be at least 512 master clock cycles between consecutive rising edges of enb1. this condition also holds true for enb2. 2. the enb1 strobe must alternate with the enb2 strobe. violation of these requirements ma y cause noise on the output channels. figure 10 - data throughput applications figure 11 depicts an isdn line card utilizing a ?u? interface transceiver and zl38010 adpcm transcoder. this central office application implements the network end of a pair-gain system. figure 12 shows zarlink devices used to construct the remote pair-gain loop terminator. pcmi1/2 adpcmo enb1 or enb2 f0i ms1 or 4 where ms2, 3, 5, 6 = 0 frame n-1 frame n frame n+1 pcm byte " x " latched into device during frame n-1 pcm byte " x " processed according to msn input states latched during frame n adpcm word " x " output from device during frame n+1 32 kbps 24 kbps 32 kbps this diagram shows the conversion sequence from pcm to adpcm. the same pipelining occurs in the reverse adpcm to pcm direction. total delay from data input to data output = 2 frames. byte "x" word "x"
zl38010 data sheet 18 zarlink semiconductor inc. figure 11 - isdn line card with 32 kbps adpcm figure 13 depicts an adpcm to linear pcm converter for applications where further, value added, functions are being performed via digital signal processor. access to linear coded pcm reduces the overhead of the dsp by removing the need for a companded to linear conversion. the linear pcm capability of the adpcm transcoder in conjunction with the frame alignment signal en1 allows dire ct connection to the serial port of both motorola and texas instruments digital signal proces sors. daisy-chaining via t he delayed frame strobe output ensures that the adpcm array is distributed over the co mplete 2048 kbit bandwidth. if the dsp has a second serial port then access to the processed pcm can be had directly. for processors with only one serial port the mt8920 connected to the dsp parallel port will provide serial access by parallel to serial conversion. the sa me daisy-chained arrangement of quad adpcm transcoders will provide a general system resource for pcm-adpcm conversion by setting the device to non-linear operation. lin- f0b c4b f0od dsto dsti i s d n ? u ? lin+ lout+ lout- mt89l80 dx st1o st1i c4i f0i f0i f0od c4i 1 2 8 pcmi1 pcmo2 f0i f0od c4i adpcmi adpcmo pcmi1 pcmo1 mclk f0i zl38010 pcmi2 pcmo2 st2o st2i pcmi2 pcmo1 pcmi1 pcmo2 f0i f0od c4i pcmi2 pcmo1 pcmi1 pcmo2 f0i f0od c4i pcmi2 pcmo1 t r 2 tr 1 t r 8 c4i f0i i n t e r f a c e
zl38010 data sheet 19 zarlink semiconductor inc. figure 12 - pair gain remote term inal utilizing zarlink components 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 vbias vref pwrst ic a/ /irq vssd cs sclk data1 data2 dout din stb/f0i clockin vdd hspkr- m+ m- vssa hspkr+ 15 16 24 23 22 21 20 19 18 17 28 27 26 25 mt9172 isnd ?u? \ 3.3v 3.3v 3.3v 3.3v 8 or zl38010 mt91l60 mt91l60 mt91l60 mt91l60 3.3v 3 3 3 16 serial micro-port intel mcs-51 motorola spi nat semi microwire static control: slic functions optional qadpcm functional control microcontroller 1 dsto dsti f0b c4b -5v 5v -24vdc meter signal i/p meter signal i/p 120vdc ring voltage 120vdc ring voltage 16 control/status lines are: lr1/2, ese1/2, shk1/2 , rc1/2 - 8 x 2 slic?s 9 control lines for qadpcm, some optional 8 signals for microport are: data1, data2, sclk, irq , cs1 , cs2 , cs3 , cs4 d-channel access through codec1 microport 16 3 8 1 2 3 4 reset tip1 ring1 dcri dcri vdd vdd vbat vee esi2 gnd vee ring2 tip2 vbat gnd vr2 vx1 vr1 vx2 esti rf1 rf2 rf3 rg1 rg2 4 37 34 28 11 13 30 7 18 19 20 21 22 1 2 14 27 3 25 26 16 39 40 38 15 5v -5v -24vdc 5,8,9,17,23,32,33,36 10.24 mhz pair gain slic 1 pair gain slic 2 pcmo1 bclk pcmi1 linear enb2/f0od vss c2o mclk f0i pcmi2 enb1 pcmo2 en1 sel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ms1 vdd ms3 ic ms4 format ms2 pwrdn adpcmi adpcmo ms6 en2 a/ ms5 interface
zl38010 data sheet 20 zarlink semiconductor inc. figure 13 - st-bus to dsp platform clkr clkx f s r f s x i r q 0 dr dx system frame pulse system 4.096 mhz s t p a 2nd serial port if available stpa port adpcm bus ti dsp c2o f0i mclk (c4i ) pcmo1 pcmo2 adpcmo adpcmi pcmi1 pcmi2 linear en1 enb2/f0o d c2o f0i mclk (c4i ) pcmo1 pcmo2 adpcmo adpcmi pcmi1 pcmi2 linear en1 enb2/f0o d c2o f0i mclk (c4i ) pcmo1 pcmo2 adpcmo adpcmi pcmi1 pcmi2 linear en1 enb2/f0o d c2o f0i mclk (c4i ) pcmo1 pcmo2 adpcmo adpcmi pcmi1 pcmi2 linear en1 enb2/f0o d zl38010 zl38010 zl38010 zl38010 +3.3v +3.3v +3.3v +3.3v st-bus mt8920
zl38010 data sheet 21 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * dc electrical characteristics are over recommended temperature and supply voltage. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd -v ss -0.3 7.0 v 2 voltage on any i/o pin v i | v o v ss -0.3 v dd + 0.3 v 3 continuous current on any i/o pin i i | i o 20 ma 4 storage temperature t st -65 150 c 5 package power dissipation p d 500 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply voltage vdd 3.0 3.3 3.6 v 2 cmos input high voltage 3.0 v dd v 3 cmos input low voltage v ss 0.5 v 4 operating temperature t a -40 +85 c dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current i cc i dd 100 4.5 a ma pwrdn = 0 pwrdn = 1, clocks active 2 input high voltage (cmos) v ih 2.0 v 3 input low voltage (cmos) v il 0.8 v 4 input leakage current i ih /i il 0.1 10 av in =v ss to v dd 5 high level output voltage v oh 2.4 v i ol =2.5 ma typically 6 low level output voltage v ol 0.4 v i ol =5.0 ma typically 7 high impedance leakage i oz 110 av in =v ss to v dd 8 output capacitance c o 10 pf 9 input capacitance c i 8pf 10 p w r d n positive threshold voltage hysteresis negative threshold voltage v+ v h v- 1.8 1.0 1.4 v v v
zl38010 data sheet 22 zarlink semiconductor inc. ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical ch aracteristics ? - serial pcm/adpcm interfaces (see figure 14) voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 bclk clock high t bch 80 ns 2 bclk clock low t bcl 80 ns 3 bclk period t bcp 200 7900 ns 4 data output delay (excluding first bit) t dd 95 ns 5 output active to high z t ahz 95 ns 6 strobe signal setup t sss 80 t bcl - 80 ns 7 strobe signal hold t ssh 80 t bcl - 80 ns 8 data input setup t dis 50 ns 9 data input hold t dih 50 ns 10 strobe to data delay (first bit) t sd 95 ns 11 f0i setup t f0is 50 122 150 ns 12 f0i hold t f0ih 50 122 150 ns 13 mclk (c4i ) duty cycle t h /t l x100 40 50 60 % 14 f0od delay t dfd 60 ns 15 f0od pulse width t dfw 244 ns 16 mclk (c4i ) period t c4p 61 244.2 ns 17 data output delay t dsd 80 120 ns 18 data in hold time t dsh 50 ns 19 data in setup time t dss 50 ns
zl38010 data sheet 23 zarlink semiconductor inc. figure 14 - serial port timing bclk enb1 or enb2 pcmi/adpcmi pcmo/adpcmo mclk f0i s s i s t - b u s t bcp t bch t bcl t sss t ssh t dis t dih t dss t dsh t dd t ahz t dsd t h t f0ih t l t c4p t dfd v ih v il v ih v il v ih v il v oh v ol v ihc v ilc v ih v il t sd v oh v ol t f0is t dfd f0od
zl38010 data sheet 24 zarlink semiconductor inc. figure 15 - st-bus timing for external signal generation ac electrical ch aracteristics ? - st-bus c2o conversion voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 delay mclk falling to c2o rising t d1 100 ns 150 pf//1 k load 2 delay mclk falling to enable t d2 100 ns 150 pf//1 k load f0i mclk (c4i ) c2o en1 en2 t d1 t d2 t d2 v ih v il v ihc v ilc v oh v ol v oh v ol
zl38010 data sheet 25 zarlink semiconductor inc. ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 16 - ssi mode sele ct set-up and hold timing figure 17 - st-bus mode select set-up and hold timing ac electrical characteristics ? - mode select timing (see figures 16 & 17) voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 mode select setup t su 500 ns mclk=4096 khz 2 mode select hold t hold 500 ns t su t hold enb1 (input) ms1 to ms6 v ih v il v ih t su t hold ms1 to ms6 mclk f0i refer to figure 14 for st-bus f0i timing. v ih v il

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